1. Field of the Invention
The present invention relates to an apparatus for ATM (Asynchronous Transfer Mode) communication, and specifically to an ATM switch for performing cell exchange in ATM communication.
2. Description of the Background Art
Recently, ISDN (Integrated Services Digital Network) providing various communication services such as telephone, data communication, circuit exchange and packet switching in an integrated manner has been practically used. Broadband ISDN has been studied to improve the speed of communication in the ISDN and to provide wider variety of communication services to be handled in the future.
In the broadband ISDN, an interface having more than one hundred times the transmission capacity of existing ISDN is used. The network is integrated in accordance with a new communication method called ATM (Asynchronous Transfer Mode).
The ATM is adapted for multimedia, and any terminal can be connected to the network regardless of the speed of communication and the required quality. In the ATM, every information from various terminals is treated in fixed length blocks, no matter whether the communication media is voice, image, data or the like. The block is referred to as a cell. The cell includes a header portion and a data portion. In the header portion, destination identifying information or the like is stored. By using this destination identifying information, every information is transmitted and switched in a multiplexed manner at high speed, cell by cell.
The ATM switch has a function of a core in an exchange for providing a cell, from an IN line (input port) to a desired OUT line (output port) based on the destination information in the header attached to the cell. If there are a number of such ATM switches in the exchange, each ATM switch is referred to as a unit switch.
A specific example of a conventional ATM switch will be described.
A representative example of a conventional ATM switch includes output buffer type ones and common buffer type ones. These ATM switches include a buffer memory for temporarily storing the input cell. The output buffer type ATM switch has a plurality of buffer memories provided for respective OUT lines. The common buffer type ATM switch includes one buffer memory provided in common for all the OUT lines.
FIG. 37 is a block diagram showing a conventional output buffer type ATM switch. The ATM switch includes a multiplexer 1, address filters F0, F1, F2 and F3, and buffer memories M0, M1, M2 and M3.
Multiplexer 1 receives cells input from IN lines I0, I1, I2 and I3, respectively. Address filters F0 to F3 are provided corresponding to OUT lines O0, O1, O2 and O3, respectively. Buffer memories M0 to M3 are also provided for OUT lines O0 to O3, respectively. Each of the buffer memories M0 to M3 is an FIFO memory.
The operation of the ATM switch shown in FIG. 37 will be described. Cells are input from IN lines I0 to I3, respectively, to multiplexer 1. Multiplexer 1 time-divisionally multiplexes and outputs the input cells. Address filters F0 to F3 each fetch only the cell having destination information of the corresponding OUT line, of the cells output from multiplexer 1. Address filters F0 to F3 apply the fetched cells to corresponding buffer memories M0 to M3, respectively. Buffer memories M0 to M3 write, in the order of arrival, the cells applied from corresponding address filters F0 to F3 and successively read the written cells to the corresponding OUT lines O0 to O3, respectively. In the output buffer type ATM switch as described above, buffer memories M0 to M3 are provided for OUT lines O0 to O3, respectively. Therefore, there is not a blocking caused between the OUT lines, achieving high throughput. Further, since buffer memories M0 to M3 can be implemented by the FIFO memories, control is easy.
The conventional common buffer type ATM switch will be described.
FIG. 38 is a block diagram showing a conventional common buffer type ATM switch. The ATM switch includes a multiplexer 1, a buffer memory M, a demultiplexer 2, a header extracting circuit 3, an empty address queue 4, address queues AQ0, AQ1, AQ2 and AQ3, a write data bus WB, a read data bus RB and a control circuit C7.
Multiplexer 1 receives cells input through IN lines I0 to I3. Common buffer memory M is provided commonly for all OUT lines O0 to O3. A cell output from multiplexer 1 is written to the common buffer memory M. Demultiplexer 2 provides cells read from common buffer memory M to OUT lines O0 to O3.
Header extracting circuit 3 is connected between each of the IN lines I0 to I3 and control circuit C7. Control circuit C7 is connected also to common buffer memory M and empty address queue 4 in addition to header extracting circuit 3, and further to address queues AQ0 to AQ3 through write data bus WB and read data bus RB, respectively.
The operation of the ATM switch shown in FIG. 38 will be described.
Cells are input from IN lines I0 to I3 to multiplexer 1, respectively. Multiplexer 1 time-divisionally multiplexes the input cell and applies the same to common buffer memory M. Header extracting circuit 3 extracts the information at the head header portion of the cell which is input to multiplexer 1, and applies the extracted information of the header portion to control circuit C7. Based on the applied information of the header portion, control circuit C7 controls writing and reading of common buffer memory M in the following manner. In empty address queue 4, an empty address of the common buffer memory M at present is written.
The aforementioned write control will be described. At the time of writing, in control circuit C7, when the extracted information of the header portion is applied, the empty address information is read from empty address queue 4. Then, the read empty address is applied as write address WA to common buffer memory M.
At the same time, control circuit C7 controls operation such that write address WA is written through write data bus WB to an address queue which corresponds to the destination OUT line indicated by the extracted header information, among the OUT line address queues AQ0 to AQ3.
In this manner, at the time of writing, cell is written to the empty address of common buffer memory M, and write address WA is written to the address queue which corresponds to the extracted information of the header portion.
Read control will be described. At the time of reading, control circuit C7 selects OUT line address queues AQ0 to AQ3 in a prescribed order, and successively reads the addresses from address queues AQ0 to AQ3 through read data bus RB. Then, control circuit C7 provides the read address as read address RA to common buffer memory M. At the same time, control circuit C7 writes read address as an empty address to empty address queue 4.
Common buffer memory M reads the cell stored at the applied read address RA and applies the cell to the demultiplexer 2. Demultiplexer 2 outputs the applied cell to the corresponding one of OUT lines O0 to O3.
In this manner, at the time of reading, cell is read from the common buffer memory in accordance with the read address RA read from OUT line address queues AQ0 to AQ3.
However, the above described conventional ATM switch suffers from the following problems.
First, disadvantage in the output buffer type ATM switch will be described. In the output buffer type ATM switch, when the destination of cells input from IN lines I0 to I3 concentrate on a specific OUT line, the capacity of the buffer memory corresponding to the OUT line may be used up, resulting in disposal of the cells. Here, the disposal of a cell means that the cell which is input to the ATM switch is not written in the buffer memory but discarded.
A possible method of avoiding such disposal of cells is to increase capacity of each buffer memory. However, this leads to increase in hardware amount of the ATM switch.
The disadvantage of the common buffer type ATM switch will be described. In the common buffer type ATM switch, when the destinations of cells input from IN lines concentrate on a specific OUT line, the remaining capacity of the OUT line address queue corresponding to the OUT line may be used up, resulting in disposal of the cells.
One possible method of avoiding such disposal of cells is to make the depth of each OUT line address queue equal to the number of addresses of the buffer memory. However, this method results in increase in hardware amount of the OUT line address queue.